Search - rs232 verilog

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以
Platform: | Size: 10421 | Author: 陈强 | Hits:

[Other resource] rs232

Description: dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.
Platform: | Size: 122378 | Author: pp | Hits:

[VHDL-FPGA-Verilog] 很好的RS232源代码

Description: 用verilog语言写的串口程序。
Platform: | Size: 3947708 | Author: noreasona | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232的一个verilog程序。
Platform: | Size: 383623 | Author: xuyuanzhi0101@126.com | Hits:

[SourceCode] rs232的verilog程序

Description: 串口的一个verilog程序。
Platform: | Size: 259722 | Author: xuyuanzhi0101@126.com | Hits:

[SCM] 51serialinterfaceapplication

Description: 51单片机模拟串口，硬件串口，rs232串口例程-51 microcontroller serial simulation, hardware serial port, RS232 serial port routines
Platform: | Size: 196608 | Author: 吕丽娟 | Hits:

[VHDL-FPGA-Verilog] async--RS232

Description: async--RS232VERILOG HDL原代码-async-- RS232VERILOG HDL source
Platform: | Size: 3072 | Author: chenxiao | Hits:

[Post-TeleCom sofeware systems] rs232_send

Description: rs232 vhdl程序可以实行异步串行通信,这里只有send-rs232 vhdl procedures implemented asynchronous serial communication, here only send
Platform: | Size: 1024 | Author: 李湘宏 | Hits:

Description: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Platform: | Size: 5120 | Author: 陈想 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[SCM] RS485

Description: 用VERILOG语言写的RS485通信程序,经调试可以直接使用-Verilog language used to write the RS485 communication program, the debugger can be used directly
Platform: | Size: 653312 | Author: 李俭 | Hits:

[Program doc] async_transmitter

Description: 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
Platform: | Size: 1024 | Author: su | Hits:

[Com Port] async_transmitter

Description: RS232串口发送模块，verilog编写，可综合-async_transmitter verilog module
Platform: | Size: 1024 | Author: Gbb | Hits:

[Other] S7_PS2_RS232

Description: 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
Platform: | Size: 1438720 | Author: wphyl | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 异步串行传输的verilog hdl 功能文件以及测试文件-The verilog hdl source and the testbench of asynchronous serial transmission
Platform: | Size: 10240 | Author: 朱红 | Hits:

[Other] deep_LabVIEW_FPGA

Description: NI 通过LabVIEW FPGA 模块和可重复配置I/O(RIO)硬件设备，为测量和控制系统中整合FPGA 技术的灵活性提供了直观且现成可用的解决方案。您可以使用LabVIEW图形化编程定义FPGA 芯片上的逻辑功能，您不需要任何的有关底层硬件描述语言(HDLs)的知识，如VHDL 或是Verilog，也不需要了解板卡级硬件设计，就可以将FPGA 芯片嵌入到NI 可重复配置I/O 系列硬件目标当中。另外，LabVIEW还可以让您轻松地集成图象采集/分析、运动控制，以及CAN 和RS232 等工业通信功能。-Through the LabVIEW FPGA Module and NI reconfigurable I/O (RIO) hardware device, for measurement and control systems integrate the flexibility of FPGA technology provides the intuitive and readily available solution. You can use the LabVIEW graphical programming custom FPGA logic functions on a chip, you do not need any of the underlying hardware description languages (HDLs) knowledge, such as VHDL or Verilog, do not need to understand the board-level hardware design, it can be FPGA chip embedded into the NI reconfigurable I/O family of hardware Goals. In addition, LabVIEW also allows you to easily integrate image capture/analysis, motion control, as well as CAN and RS232 communication industries.
Platform: | Size: 274432 | Author: 侯yl | Hits:

[VHDL-FPGA-Verilog] S7_PS2_RS232

Description: 基于verilog语言PS2接口和RS232接口的实现-PS2 based on verilog language interface and RS232 interface implementation
Platform: | Size: 1748992 | Author: jiehao | Hits:

[VHDL-FPGA-Verilog] PS2andRS232

Description: 基于Verilog语言PS2接口和RS232接口的实现有文档说明,工程实例.可用来学习Verilog语言.-Based on Verilog Language PS2 interface and RS232 interface implementation are documented, project examples. Can be used to learn the Verilog language.
Platform: | Size: 1770496 | Author: generalj | Hits:

[VHDL-FPGA-Verilog] uart

Description: RS232控制分频,实现占空比和频率可以控制的分频器-verilog RS232
Platform: | Size: 79872 | Author: cuiqiang | Hits:

[VHDL-FPGA-Verilog] rs232

Description: RS232的串口控制器，本程序中的每个小模块都有与之对应的testbench，模块清晰，实现结构简单。很适合Verilog编程初学者来练习！-RS232 serial port controller, the program has a small module for each corresponding testbench, module definition, to achieve simple structure. Verilog programming is suitable for beginners to practice!
Platform: | Size: 418816 | Author: veriman | Hits:

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[Com Port] uart(Verilog)

[Other resource] rs232

[VHDL-FPGA-Verilog] 很好的RS232源代码

[VHDL-FPGA-Verilog] RS232

[SourceCode] rs232的verilog程序

[SCM] 51serialinterfaceapplication

[VHDL-FPGA-Verilog] async--RS232

[Post-TeleCom sofeware systems] rs232_send

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[SCM] RS485

[Program doc] async_transmitter

[Com Port] async_transmitter

[Other] S7_PS2_RS232

[VHDL-FPGA-Verilog] rs232

[Other] deep_LabVIEW_FPGA

[VHDL-FPGA-Verilog] S7_PS2_RS232

[VHDL-FPGA-Verilog] PS2andRS232

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] rs232

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